1. Field of the Invention
The present invention relates to the manufacturing of a bipolar transistor in integrated circuits. More specifically the present invention relates to the forming of base and emitter regions of a bipolar transistor in a BICMOS technology.
2. Discussion of the Related Art
Bipolar transistor manufacturing methods that provide delimiting active areas on a semiconductor substrate, depositing a base contact polysilicon coated with a silicon oxide layer, opening a base/emitter area, forming spacers on the opening walls, and depositing an emitter contact polysilicon layer, will be considered. In the context of these methods, the forming of spacers is more specifically considered herein.
In various conventional methods, oxide, nitride, or nitride/polysilicon spacers are used. Each of these methods has advantages and disadvantages. A method in which compound nitride/polysilicon spacers are used will first be described in detail to show their advantages and disadvantages. The advantages and disadvantages of other known spacer types will then briefly be mentioned.
Nitride/Polysilicon Spacers
As illustrated in FIG. 1A, the first steps of a bipolar transistor manufacturing method consist of defining, at the surface of a semiconductor substrate 1, typically made of silicon, active areas delimited by field oxide areas 2. Then, a polysilicon layer 4, intended for forming the base contact, and an insulating layer 5, typically made of silicon oxide, are successively deposited.
At the next steps, illustrated in FIG. 1B, layers 5 and 4 are etched to expose a substantially central portion of the active area. An anneal is then performed, which in particular causes the forming of a silicon oxide layer 6 at the bottom of the window and on the lateral surface of polysilicon layer 4. A dopant of a first conductivity type, for example, type P, typically, boron, is implanted to form base 3i of the bipolar device. A base contact area 3e resulting from a diffusion of the dopants contained in polysilicon layer 4 has also been shown.
At the next steps, illustrated in FIG. 1C, spacers are formed. For this purpose, a silicon nitride layer 7 is conformally deposited. Then, a polysilicon layer is deposited and etched to form spacers 8 such as shown in FIG. 1C.
At the next steps, illustrated in FIG. 1D, silicon nitride layer 7 is removed everywhere it is not protected by spacers 8, and the bottom of the window is cleaned to expose base region 3. Finally, an emitter contact layer 9, typically made of polysilicon, is deposited. Layer 9 then undergoes an implantation of an N-type dopant that diffuses to form an emitter region 10.
A base/emitter junction between an emitter region 10 and a base region 3 has thus been formed, the distance between the base and emitter contacts being defined by compound spacers formed of thermal oxide 6, silicon nitride 7, and polysilicon 8.
FIG. 1D clearly shows the functions that the spacer has to perform and the qualities that it must have.
1) The spacer must ensure good insulation between polysilicon layers 4 and 9. This insulation is essentially ensured by nitride layer 7. However, given the very small thickness of layer 7 and the silicon nitride etch properties, layer 7 is overetched under polysilicon 8, as illustrated in FIG. 1D. This overetching results in various disadvantages: the formed cavity will be poorly filled by polysilicon 9 and it creates a heterogeneity that can be a source of mechanical stress and in any case of poor control of the manufacturing process.
2) The capacitance between base polysilicon region 4 and emitter region 9 must be as small as possible. Indeed, it is generally desired for the bipolar transistor to switch rapidly. This result is not obtained. Indeed, polysilicon 8 is conductive and the silicon nitride is very thin and has a high dielectric constant.
3) The distance between the foot (the area of contact with the substrate) of polysilicon 4 and the foot of polysilicon 9, as well as the surface of the contact between polysilicon 9 and the substrate must be precisely determined and be reproducible. A priori, the polysilicon spacers have a clear-cut shape and straight edges. However, the etching of oxide layer 6 is not always ideal. Indeed, due to the poor wetability between polysilicon and any etch solution, bubbles can form at the bottom of the window, at the level of the spacer angle, which results in a poor removal of layer 6 at this location, as illustrated in FIG. 1D. Similarly, the subsequent washing with deionized water, intended for removing the etch residue and the excess hydrofluoric acid, will not be perfect. Malfunctions of the device may result therefrom.
4) The opening defined by the spacer and into which polysilicon 8 penetrates must preferably be flared enough to ease the subsequent doping of this polysilicon by implantation and to reduce access resistances. This result is obviously not obtained with the spacers of FIG. 1D, the anisotropic etching of the polysilicon being practically vertical.
5) There must exist no differential stress between the spacer and the underlying substrate. This object is properly fulfilled by a nitride/polysilicon spacer.
Silicon Nitride Spacers
It has also been attempted to use nitride spacers. However, significant technological difficulties arise when forming sufficiently thick spacers. These spacers have all the disadvantages discussed at points 1) to 4) relative to nitride/polysilicon spacers. Further, as concerns point 5), they generally generate differential stress.
Silicon Oxide Spacers
Simple silicon oxide spacers have a very rounded upper corner and sides slightly diverging outwards. They are thus preferable as concerns point 4). Also, as concerns point 2), these spacers are satisfactory since they can be relatively thick and the dielectric constant of SiO2 is much smaller than that of Si3N4.
As concerns points 1) and 3), these spacers have significant disadvantages.
Besides, upon etching of the spacers, silicon oxide based polymers form at the exposed surface of the substrate. These polymers will be difficult to eliminate. Indeed, it is not possible to wash them off by means of hydrofluoric acid, since there would then be a risk to overetch the spacers, also made of silicon oxide, and thus to increase the opening width, which is not desirable.
Especially as concerns point 5), another disadvantage of silicon oxide spacers is the generation of thermal expansion stress between the oxide and the underlying silicon. This disadvantage is in particular underlined in patent application EP-A-0746032 assigned to Matsuhita Electronics Corporation. This document, which advocates the use of oxide or nitride/oxide spacers for MOS transistors of a BICMOS structure, indicates that thermal stress problems forbid the use of such spacers for bipolar transistors and advocates the use of compound nitride/polysilicon spacers for such transistors, which greatly complicates the manufacturing method.
An object of the present invention is to provide a novel method of manufacturing bipolar transistors that overcomes one or several of the disadvantages of the various known methods.
Another object of the present invention is to provide such a method that reduces the resistance of the base-emitter junction.
Another object of the present invention is to provide such a method that is simple to implement, in particular in a BICMOS technology.
To achieve these and other objects, the present invention provides a method of manufacturing a bipolar transistor in a semiconductor substrate of a first conductivity type, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a dopant of the second conductivity type; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting a dopant of the first conductivity type.
According to an embodiment of the present invention, the step of doping the first polysilicon layer includes performing a low-energy implantation to initially concentrate the dopant atoms in the upper portion of the first polysilicon layer.
According to an embodiment of the present invention, the cleanings include a cleaning an acid matter, a cleaning under oxygen plasma and a wet cleaning.
According to an embodiment of the present invention, the third thin oxide layer has a thickness on the order of 5 nm.
According to an embodiment of the present invention, the fourth silicon nitride layer has a thickness on the order of 30 nm.
According to an embodiment of the present invention, the fifth silicon oxide layer has a thickness on the order of 150 nm.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.